next up previous
Next: Reference Up: Low Frequency Receiver Circuit Previous: Low Frequency Receiver Circuit

Design and Comments

The receiver for the solar flare monitor is a simple circuit designed to detect the 24 KHz signal from the station in Cutler, Maine, and reject signals at nearby frequencies from other directions. The receiver uses a commercial amplified loop antenna manufactured by ``Palomar'' with its ``Omega'' loop. The loop is approximate 25 cm in diameter and can be oriented in any direction. In a concrete and wood building away from significant structural iron the plane of the loop is vertical and its normal is approximately along a line directed from Louisville, KY, to Cutler, ME. This antenna has an internal FET preamp which may be battery operated. In our system the battery is not connected, and the internal circuit has been modified to accept power delivered on the coax from the antenna to the receiver. The amplified RF from the antenna is capacitively coupled to a LC resonator tuned to 24 KHz. This first stage of the receiver is shown in Fig. 1.

Figure 1: The LC resonator. A preamplified signal from the antenna enters at A. This section is enclosed in a grounded box inside the receiver chassis. The station is selected by varying L2 while monitoring the output of the next stage.

The output from the LC resonator connects to an RF 2-stage amplifier shown in Fig. 2. The amplifier uses a commonly available LF353 dual JFET opamp with the first stage as a voltage follower of unity gain, and the second stage with gain $(R_1 + R_2)/R_1 \approx 101$ in this example. The output of this amplifier may be fed directly to an oscilloscope to monitor tuning of the LC circuit and the antenna.

Figure 2: The signal B from the LC circuit enters a voltage follower (U1A) and is then capacitively coupled to an amplifier (U1B). The output goes to an oscilloscope (C) for tuning, and to a detection circuit (D).

The RF amplifier is capacitively coupled to a detector circuit that rectifies the 24 KHz signal and provides some additional gain. This section also uses an LF353 as shown in Fig. 3.

Figure 3: The amplified 24 KHz signal enters at D, is capacitively coupled to the first stage (U2A), rectified by D1 and D2, amplified by a second stage (U2B) and connected to an output amplifer at E.

Additional gain, low-pass filtering, and buffering is provided by a third dual JFET opamp in the section shown in Fig. 4. The gain is adjusted by the resistor R9, which is omitted for $1\times$ or decreased to 10K for $100\times$. In this version it is set to $225\times$. The time constant is R11$\times$C5 and is set to 5 s here. The resistor R12 provides some output loading of the amplifier and is adjusted to minimize noise. It leads to a BNC jack on the front panel of the amplifier and a 50 $\Omega$ cable connects from there to the analog-to-digital converter at the computer. An additional RC filter is located at the A-to-D to properly terminate this cable and minimize noise.

Figure 4: A halfwave rectified signal from the detector enters at E and is amplified by U3A. The time constant is set by adjusting R11 and the output is buffered with the voltage follower U3B.

next up previous
Next: Reference Up: Low Frequency Receiver Circuit Previous: Low Frequency Receiver Circuit